Manufacturing tolerances in power semiconductor packaging introduce significant thermal performance variability, complicating the distinction between acceptable process scatter and critical defects. Traditional Finite Element Method (FEM) analysis and 135ter measurements often rely on deterministic nominal dimensions, failing to account for the highly non-linear relationship between geometric parameters and the corresponding thermal structure function.

This study proposes a high-speed probabilistic framework utilizing Deep Operator Networks (DeepONet) to map the function space between package design parameters and their corresponding thermal structure functions. The DeepONet surrogate model achieves a 3,100× computational acceleration compared to conventional FEM, enabling real-time generation of theoretical structure functions for any given set of process variables. By integrating this model with Metropolis-Hastings MCMC sampling, we derive a 99.7% confidence band (3σ) that serves as a dynamic pass/fail criterion for anomaly detection.

Beyond forward prediction, we introduce an Inverse Design and Sensitivity Analysis (Step B). Leveraging the differentiability of the DeepONet's Trunk Net, we utilize gradient-based backpropagation to estimate internal geometric deviations (e.g., bond-line thickness, void size) directly from measured thermal data. This inverse framework identifies which specific design parameters contribute most significantly to pushing the structure function outside the nominal operating band. Case studies on solder voiding and complex geometric offsets demonstrate that the proposed sensitivity analysis can pinpoint root causes of thermal degradation non-destructively.

This framework provides a scalable Digital Twin solution for proactive quality control and autonomous process optimization in high-volume semiconductor manufacturing.